Many electronic systems have low power states, sometimes known as “sleep” states or “off states” although more generally there is now a spectrum of power down levels with reduced power level in addition to a “normal” operating state. For example, modern computer systems and graphics systems typically place different units and interfaces into a low power down state when specific units and interfaces are idle. For example, a microprocessor may have power states C0-C3, where C0 is the operating state, C1 is a halt state, C2 is stop-clock state, and C3 is sleep state. Some microprocessors also have deep sleep (C4) and/or deeper sleep states that differ in how long it takes to wake up the processor. Some buses, such as the HyperTransport (HT) bus facilitate power management such that changes in processor state can signal changes to a lower power HT device state. As other examples, the voltage of a memory controller can be reduced when idle, PHY interfaces may have different power down levels, and phase locked loops can be turned off when in idle states.
As examples of power down states, a voltage of an integrated circuit, such as a central processing unit or memory controller, may be placed into low-voltage state as an ultra low power state for an idle condition. As one example, some AMD based processors support a low power mode in which a CPU clock or voltage can be ramped down to save power. Additionally, an Alternate Voltage ID (AltVID) option in some AMD microprocessors permits chip voltage to be ramped down further after the clocks have ramped down. The AltVID option includes a programmable code sent to a voltage regulator to reduce microprocessor voltage to a minimum operational level for additional power savings. PHY network interfaces may have a low power state for an idle condition. Additionally, in some systems portions of the clock tree feeding idle units, such as phase locked loops, may be turned off in an idle state. Thus, in light of recent advances in power savings technology, systems designers often have two or more possible choices for a power down state that correspond to a sleep state and at least one “deeper sleep” state. That is, in designing an electronic system, a designer chooses one of two or more low power states (“power down”) levels as the default power down state that the system enters for an idle condition. However, each power down level also has an associated exit latency to transition to a normal mode of operation when the system is fully functional. The deeper power down levels have better power savings but also have higher exit latencies, i.e., require a longer time to wake up. Conventionally, a deep power down state, such as one using AltVID, cannot be used if the system includes units having a latency tolerance less than the exit latency of the deep power down state. Conventionally a system designer would select a default power down state based on a worst case latency tolerance.
However, in many systems there are may be a variety of units with different latency tolerances. For example, a graphics system may have an integrated circuit designed to perform many different functions. For example, the Media and Communications Processors (MCPs) developed by the Nvidia Corporation of Santa Clara, Calif. replaces a conventional Southbridge chip and supports integrated networking and communications functions such as supporting Ethernet ports, universal serial bus (USB) ports, audio processing, and Dolby digital encoding. Each of these different functions has a corresponding unit with a latency tolerance. Conventionally, it is desirable to increase the number of different integrated networking and communications functions in an MCP chip to increase the number of available functions. However, this makes it difficult using conventional design approaches to utilize deeper power down levels using the conventional design approach.
Therefore, in light of the problems described above, the apparatus, method, and system of the present invention was developed.